Device and method for stress testing a semiconduction memory

ABSTRACT

A DRAM is stress tested by writing a logic bit in a weakened state from a sense amplifier of the DRAM to a sub-array of the DRAM. This is accomplished by reducing an upper rail voltage supplied to a P-sense amp in the sense amplifier and increasing a lower rail voltage supplied to an N-sense amp in the sense amplifier, or by operating isolation NMOS transistors through which a differential voltage representative of the logic bit passes from the sense amplifier to the sub-array at less than a full activation level. Once the logic bit is written to the sub-array in a weakened state, it is then read back out to stress the DRAM and thereby identify weak sense amplifiers and DRAM cells in the DRAM.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of application Ser. No. 09/026,245, filed Feb. 19, 1998, now U.S. Pat. No. 5,959,913.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates in general to semiconductor memories such as Dynamic Random Access Memories (DRAMs) and, more specifically, to stress testing of such memories.

2. State of the Art

DRAMs are typically subjected to stress testing during manufacturing. Such testing, also referred to as margin testing, includes various procedures for identifying DRAM cells that are unable to store sufficient charge (referred to as "weak" cells) and for identifying sense amplifiers that lack sufficient sensitivity or gain (referred to as "weak" sense amplifiers).

One conventional method for stress testing DRAMs involves reducing their supply voltage during testing. This reduces the charge that can be written to their memory cells and also reduces the gain of their sense amplifiers. Weak memory cells are then identified by misreads resulting from the reduced charge written to the cells. Also, weak sense amplifiers are identified by misreads resulting from their lacking the necessary sensitivity or gain to correctly read the reduced charge written to the memory cells.

With the increasing use of 2.0 volt DRAM process technology, it is becoming clear that a new device and method for stress testing DRAMs is needed. This is because peripheral circuitry in 2.0 volt DRAMs, which is necessary for external testing equipment to interact with the DRAMs during stress testing, typically begins to shut down at a supply voltage of about 1.5 volts, so that reducing the supply voltage of such DRAMs significantly below 2.0 volts is not a viable means of stress testing the DRAMs.

Therefore, there is a need in the art for a new device and method for stress testing DRAMs and other semiconductor memories. Such a device and method should provide a viable means for testing 2.0 volt DRAMs.

SUMMARY OF THE INVENTION

In accordance with the invention, a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), is stress tested by writing a logic bit in a weakened state from a sense amplifier of the semiconductor memory to a memory array of the semiconductor memory. This can be accomplished by reducing the rail-to-rail potential of the sense amplifier, such as by reducing an upper rail voltage supplied to a P-sense amp in the sense amplifier and increasing a lower rail voltage supplied to an N-sense amp in the sense amplifier. Alternatively, it can be accomplished by operating isolation switches through which a differential voltage representative of the logic bit passes from the sense amplifier to the memory array at less than a full activation level, thereby reducing the differential voltage passed to the memory array through the isolation switches. When the isolation switches are NMOS transistors, for example, the differential voltage decreases as a result of the latter method by at least a threshold voltage of one of the transistors as it passes through on its way to the memory array. Once the logic bit is written to the memory array in a weakened state, it is then read back out so the weakened state of the bit stresses the semiconductor memory.

Thus, the invention stress tests DRAMs and other semiconductor memories in a new way that is suitable for 2.0 volt DRAMs because it does not require the reduction in their supply voltage that can be a problem for the conventional stress testing method previously described.

In accordance with another embodiment of the invention, a device for stress testing a semiconductor memory includes circuitry for causing a sense amplifier of the semiconductor memory to operate as described above.

In still further embodiments of the invention, a semiconductor memory, an electronic system, and a semiconductor wafer incorporate the previously described inventive device.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram and circuit schematic of a Dynamic Random Access Memory (DRAM) including a pair of sub-arrays and their associated sense amplifier implementing the invention;

FIGS. 2A and 2B are graphs of signals that cause the sense amplifier of FIG. 1 to operate in accordance with the invention;

FIG. 3 is a block diagram of circuitry for generating some of the signals of FIGS. 2A and 2B;

FIG. 4 is a circuit schematic showing the circuitry of FIG. 3 in more detail;

FIG. 5 is a block diagram of an electronic system incorporating the DRAM of FIG. 1; and

FIG. 6 is a diagram of a semiconductor wafer on which the DRAM of FIG. 1 is fabricated.

DETAILED DESCRIPTION OF THE INVENTION

As shown in FIGS. 1 and 2A, a Dynamic Random Access Memory (DRAM) 10 begins a stress test read cycle in accordance with the invention in a steady state at time t₀ with a pair of isolation signals ISOa* and ISOb* fully activating two pairs of isolation NMOS transistors 12 and 14 in a sense amplifier 16 of the DRAM 10 with a wordline voltage V_(CCP) (typically about 3.7 volts in a 2.0 volt DRAM). The activated transistors 12 and 14 provide a conductive path between complementary sense nodes SA and SA* of the sense amplifier 16 and sub-arrays 18 and 20 of the DRAM 10 along complementary bitlines BLa, BLa*, BLb, and BLb*. At the same time, a pair of equalization signals EQa and EQb are activating equalization NMOS transistors 22 and 24 to equalize voltages on the bitlines BLa, BLa*, BLb, and BLb* and on the sense nodes SA and SA* to an intermediate voltage DVC2 that is equal to one half of a supply voltage V_(CC) supplied to the DRAM 10. It will be understood by those having skill in the field of this invention that although the invention will be described with respect to a DRAM, it is also applicable to other semiconductor memories such as a Synchronous Dynamic Random Access Memory (SDRAM) requiring stress testing.

When the sub-array 18, for example, is to be stress tested, the isolation signal ISOb* drops during a time period t₁, to deactivate isolation NMOS transistors 14, thereby isolating the sense nodes SA and SA* of the sense amplifier 16 from the sub-array 20. The equalization signal EQa also drops to deactivate the equalization NMOS transistors 22, thereby allowing the bitlines BLa and BLa*, and hence the sense nodes SA and SA*, to take on voltages independently of one another.

At a time t₂, a rising wordline WL of the sub-array 18 accesses a DRAM cell (not shown) in the sub-array 18. The DRAM cell then dumps its stored charge representative of a logic "1" bit, for example, onto the bitline BLa, causing the voltage on the bitline BLa and the voltage on the sense node SA to rise by about 200 mV.

During a time period t₃, a dropping isolation signal ISOa* deactivates isolation NMOS transistors 12, thereby isolating the sense nodes SA and SA* from the bitlines BLa and BLa*. A dropping lower rail voltage NLAT* also causes NMOS transistors 26 of an N-sense amp 28 of the sense amplifier 16 to pull the sense node SA* low. Similarly, a rising upper rail voltage ACT causes PMOS transistors 30 of a P-sense amp 32 of the sense amplifier 16 to pull the sense node SA high. Once the sense nodes SA and SA* are separated by the N-sense amp 28 and the P-sense amp 32, a column selection signal CSEL activates column select NMOS transistors 34 to drive the separated voltages on the sense nodes SA and SA* onto an internal data bus I/O and I/O* of the DRAM 10, where they are output to external circuitry (see FIG. 5).

During a time period t₄, the column selection signal CSEL drops to deactivate the column select NMOS transistors 34, thereby isolating the sense nodes SA and SA* from the internal data bus I/O and I/O*. Also, the isolation signal ISOa* rises back to the wordline voltage V_(CCP) to reactivate the isolation NMOS transistors 12, thereby reopening a conductive path between the sense nodes SA and SA* and the bitlines BLa and BLa*.

Further, the upper rail voltage ACT drops to a voltage V_(UPPER), causing the sense node SA to drop, and the bitline BLa to rise, approximately to the voltage V_(UPPER). At the same time, the lower rail voltage NLAT* rises to a voltage V_(LOWER), causing the sense node SA* to rise, and the bitline BLa* to drop, approximately to the voltage V_(LOWER). The voltages V_(UPPER) and V_(LOWER) on the bitlines BLa and BLa* are then conducted back to the sub-array 18 for storage therein. As a result, the logic "1" bit previously read (at time t₂ above) from the DRAM cell (not shown) in the sub-array 18, and now represented by the voltages V_(UPPER) and V_(LOWER) on the bitlines BLa and BLa*, is written back to the sub-array 18 in a weakened state.

During a time period t₅, the DRAM 10 finishes its stress test read cycle and returns to its steady state. More specifically, the wordline WL drops to close off access to the DRAM cell (not shown) in the sub-array 18, the upper rail voltage ACT drops to a ground voltage V_(REF) to deactivate the P-sense amp 32, the lower rail voltage NLAT* rises to the intermediate voltage DVC2 to deactivate the N-sense amp 28, the isolation signal ISOb* returns to the wordline voltage V_(CCP) to activate the isolation NMOS transistors 14 and connect the sub-array 20 to the sense amplifier 16, and the equalization signal EQa rises to activate the equalization transistors 22 and equalize the voltages on the bitlines BLa, BLa*, BLb, and BLb* and the sense nodes SA and SA* to the intermediate voltage DVC2.

Once the logic "1" bit is stored in the sub-array 18 in a weakened state, a subsequent stress test read cycle attempts to read the weakened logic "1" bit out of the sub-array 18. When the DRAM cell storing the weakened logic "1" bit is weak, or the sense amplifier 16 is weak, a misread of the weakened logic "1" bit may occur. This misread serves to identify the weakened DRAM cell or sense amplifier 16. Of course, it should be understood that the invention also works with logic "0" bits.

Referring now to FIGS. 1 and 2B, in another embodiment of the invention, the DRAM 10 operates in the same manner as described above through time periods t₀, t₁, t₂, and t₃. During a time period t₄, the column selection signal CSEL drops to deactivate the column select NMOS transistors 34, thereby isolating the sense nodes SA and SA* from the internal data bus I/O and I/O*. Also, the isolation signal ISOa* rises to the supply voltage V_(CC) to reactivate the isolation NMOS transistors 12 at less than a full activation level. This pulls the bitline BLa up to a voltage V_(UPPER) that is below the supply voltage V_(CC) by at least a threshold voltage V_(T) of the transistors 12. At the same time, the lower rail voltage NLAT* rises to a voltage V_(LOWER), causing the sense node SA* to rise, and the bitline BLa* to drop, approximately to the voltage V_(LOWER). The voltages V_(UPPER) and V_(LOWER) on the bitlines BLa and BLa* are then conducted back to the sub-array 18 for storage therein. As a result, the logic "1" bit previously read (at time t₂) from the DRAM cell (not shown) in the sub-array 18, and now represented by the voltages V_(UPPER) and V_(LOWER) on the bitlines BLa and BLa*, is written back to the sub-array 18 in a weakened state.

During a time period t₅, the DRAM 10 finishes its stress test read cycle and returns to its steady state. More specifically, the wordline WL drops to close off access to the DRAM cell (not shown) in the sub-array 18, the upper rail voltage ACT drops to ground V_(REF) to deactivate the P-sense amp 32, the lower rail voltage NLAT* rises to the intermediate voltage DVC2 to deactivate the N-sense amp 28, the isolation signal ISOb* returns to the wordline voltage V_(CCP) to fully activate the isolation NMOS transistors 14 and connect the sub-array 20 to the sense amplifier 16, the isolation signal ISOa* returns to the wordline voltage V_(CCP) to fully activate the isolation NMOS transistors 12, and the equalization signal EQa rises to activate the equalization transistors 22 and equalize the voltages on the bitlines BLa, BLa*, BLb, and BLb* and the sense nodes SA and SA* to the intermediate voltage DVC2.

Again, once the logic "1" bit is stored in the sub-array 18 in a weakened state, a subsequent stress test read cycle attempts to read the weakened logic "1" bit out of the sub-array 18. When the DRAM cell storing the weakened logic "1" bit is weak, or the sense amplifier 16 is weak, a misread of the weakened logic "1" bit may occur. This misread serves to identify the weakened DRAM cell or sense amplifier 16.

As shown in FIG. 3, the invention includes circuitry 40, 42, and 44 for providing the isolation signal ISOa*, the upper rail voltage ACT, and the lower rail voltage NLAT* in the inventive manner illustrated in FIGS. 2A and 2B.

As shown in FIG. 4 in more detail, the isolation signal ISOa* of the circuitry 40 is active when an isolate control signal ISOLATE activates an NMOS transistor 41. When the isolate control signal ISOLATE is inactive, it turns on a PMOS transistor 43, thereby pulling the isolation signal ISOa* up to either the supply voltage V_(CC) or the wordline voltage V_(CCP), depending on whether a test activation signal TEST₁ is active and turns on a PMOS transistor 46 through an inverter 48, or is inactive and turns on a PMOS transistor 50.

The upper rail voltage ACT of the circuitry 42 is inactive when an inactive control signal PLATCH* activates an NMOS transistor 52. When the control signal PLATCH* is active, it turns on a PMOS transistor 54, thereby pulling the upper rail voltage ACT up to the supply voltage V_(CC) if an inactive test activation signal TEST₂ activates a PMOS transistor 56. Instead, if the test activation signal TEST₂ is active, it turns on a PMOS transistor 58 through an inverter 60, thereby pulling the upper rail voltage ACT up to the supply voltage V_(CC) less about a threshold voltage V_(T) drop (i.e., ACT=V_(CC) -V_(T)) caused by a diode-connected PMOS transistor 62.

The lower rail voltage NLAT* of the circuitry 44 is inactive when an inactive control signal NLATCH activates a PMOS transistor 64. When the control signal NLATCH is active, it turns on an NMOS transistor 66, thereby pulling the lower rail voltage NLAT* down to ground voltage if an inactive test activation signal (TEST₁ or TEST₂) activates an NMOS transistor 68 through an inverter 70. Instead, if the test activation signal (TEST₁ or TEST₂) is active, it turns on an NMOS transistor 72, thereby pulling the lower rail voltage NLAT* down to ground voltage plus about a threshold voltage V_(T) drop (i.e., NLAT*=ground+V_(T)) caused by a diode-connected NMOS transistor 74. It should be understood that a wide variety of other circuitry will also work in implementing the circuitry 40, 42, and 44 in the invention.

As shown in FIG. 5, an electronic system 80 includes an input device 82, an output device 84, a processor device 86, and a memory device 88 incorporating the DRAM 10 of FIG. 1. Of course, any of the input, output, and processor devices 82, 84, and 86 may also incorporate the DRAM 10 of FIG. 1.

As shown in FIG. 6, the DRAM 10 of FIG. 1 is fabricated on the surface of a semiconductor wafer 90. The wafer 90 may comprise a sliced wafer of silicon, or may comprise any other suitable substrate, including, for example, a Silicon-on-Sapphire (SOS), Silicon-on-Insulator (SOI), or Silicon-on-Glass (SOG) substrate.

Although the invention has been described with reference to particular embodiments, it is not limited to these described embodiments. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent devices or methods that operate according to the principles of the invention as described. 

What is claimed is:
 1. An electronic circuit for writing weak logic signals into a memory array of a semiconductor memory during stress testing, said electronic circuit comprising:a sense amplifier coupled between complementary sense nodes on which a differential voltage representative of a logic signal may be present; isolation circuitry coupled between said complementary sense nodes and complementary bit lines coupled to said memory array responsive to an isolation signal for selectively coupling or isolating said complementary sense nodes from said complementary bit lines; and equalization circuitry coupled between said memory array and said isolation circuitry and coupled between said complementary bit lines and responsive to an equalization signal for reducing a differential voltage which may be measured between said complementary bit lines and sensed by said sense amplifier between said complementary sense nodes during stress testing of said semiconductor memory.
 2. The electronic circuit of claim 1, wherein said sense amplifier comprises:an N-sense amplifier coupled between said complementary sense nodes; and a P-sense amplifier coupled between said complementary sense nodes.
 3. The electronic circuit of claim 2, wherein said N-sense amplifier comprises:a first NMOS transistor having a drain coupled to a first node of said complementary sense nodes, a source coupled to a lower rail voltage and a gate coupled to a second node of said complementary sense nodes; and a second NMOS transistor having a drain coupled to said second node of said complementary sense nodes, a source coupled to the lower rail voltage and a gate coupled to said first node of said complementary sense nodes.
 4. The electronic circuit of claim 2, wherein said P-sense amplifier comprises:a first PMOS transistor having a drain coupled to a first node of said complementary sense nodes, a source coupled to an upper rail voltage and a gate coupled to a second node of said complementary sense nodes; and a second PMOS transistor having a drain coupled to said second node of said complementary sense nodes, a source coupled to said upper rail voltage and a gate coupled to said first node of said complementary sense nodes.
 5. The electronic circuit of claim 1, wherein said isolation circuitry comprises:a first NMOS transistor having a drain coupled to a first node of said complementary bit lines, a source coupled to a first of said complementary sense nodes and a gate coupled to an isolation signal; and a second NMOS transistor having a drain coupled to a second of said complementary bit lines, a source coupled to node a second of said complementary sense nodes and a gate coupled to said isolation signal.
 6. The electronic circuit of claim 1, wherein said equalization circuitry comprises:a first switching element coupled between a first of said complementary bit lines and an intermediate voltage, said first switching element controlled by an equalization signal; and a second switching element coupled between a second of said complementary bit lines and said intermediate voltage, said second switching element controlled by said equalization signal.
 7. The electronic circuit of claim 6, wherein said first switching element and said second switching element are NMOS transistors.
 8. The electronic circuit of claim 6, wherein said first switching element and said second switching element are PMOS transistors.
 9. The electronic circuit of claim 6, further comprising a third switching element coupled between said complementary bit lines and controlled by said equalization signal.
 10. The electronic circuit of claim 9, wherein said third switching element is an NMOS transistor.
 11. The electronic circuit of claim 9, wherein said third switching element is a PMOS transistor.
 12. The electronic circuit of claim 1, further comprising I/O switching circuitry coupled to said complementary sense nodes for coupling said complementary sense nodes to complementary I/O lines of said semiconductor memory.
 13. The electronic circuit of claim 12, wherein said I/O switching circuitry comprises two NMOS transistors both controlled by a select signal.
 14. The electronic circuit of claim 1, further comprising:a second isolation circuit coupled between said complementary sense nodes and a second pair of complementary bit lines coupled to a memory sub-array responsive to a second isolation signal for selectively coupling or isolating said complementary sense nodes from said second pair of complementary bit lines; and a second equalization circuit coupled between said memory sub-array and said second isolation circuit and coupled between said complementary bit lines and responsive to a second equalization signal for reducing a differential voltage which may be measured between said second pair of complementary bit lines and sensed by said sense amplifier between said complementary sense nodes during stress testing of said semiconductor memory.
 15. A semiconductor memory comprising:a memory array; a sense amplifier coupled between complementary sense nodes on which a differential voltage representative of a logic signal may be present; isolation circuitry coupled between said complementary sense nodes and complementary bit lines coupled to said memory array responsive to an isolation signal for selectively coupling or isolating said complementary sense nodes from said complementary bit lines; and equalization circuitry coupled between said memory array and said isolation circuitry and coupled between said complementary bit lines and responsive to an equalization signal for reducing a differential voltage which may be measured between said complementary bit lines and sensed by said sense amplifier between said complementary sense nodes during stress testing of said semiconductor memory.
 16. The semiconductor memory of claim 15 wherein said memory array comprises a Dynamic Random Access Memory (DRAM) array.
 17. The semiconductor memory of claim 15 wherein said memory array comprises a Synchronous Random Access Memory (SDRAM) array.
 18. The semiconductor memory of claim 15, wherein said equalization circuitry comprises:a first switching element coupled between a first of said complementary bit lines and an intermediate voltage, said first switching element controlled by an equalization signal; a second switching element coupled between a second of said complementary bit lines and said intermediate voltage, said second switching element controlled by said equalization signal; and a third switching element coupled between said complementary bit lines and controlled by said equalization signal.
 19. An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, memory, and processor devices comprising a semiconductor memory including:a memory array; a sense amplifier coupled between complementary sense nodes on which a differential voltage representative of a logic signal may be present; isolation circuitry coupled between said complementary sense nodes and complementary bit lines coupled to said memory array responsive to an isolation signal for selectively coupling or isolating said complementary sense nodes from said complementary bit lines; and equalization circuitry coupled between said memory array and said isolation circuitry and coupled between said complementary bit lines and responsive to an equalization signal for reducing a differential voltage which may be measured between said complementary bit lines and sensed by said sense amplifier between said complementary sense nodes during stress testing of said semiconductor memory.
 20. A semiconductor wafer on which is fabricated a semiconductor memory comprising:a memory array; a sense amplifier coupled between complementary sense nodes on which a differential voltage representative of a logic signal may be present; isolation circuitry coupled between said complementary sense nodes and complementary bit lines coupled to said memory array responsive to an isolation signal for selectively coupling or isolating said complementary sense nodes from said complementary bit lines; and equalization circuitry coupled between said memory array and said isolation circuitry and coupled between said complementary bit lines and responsive to an equalization signal for reducing a differential voltage which may be measured between said complementary bit lines and sensed by said sense amplifier between said complementary sense nodes during stress testing of said semiconductor memory. 